With the increasing down-scaling of integrated circuits, the integrated circuits become more compact, and some restricted design rules have to be applied, which have become major limitations in the layout design. For standard cells that are frequently used in the integrated circuits, these restricted design rules cause the increase in the chip area usage, increased difficulty in the auto placement and route, and the violation in the design rule check.
Conventionally, to follow the restricted design rules, several approaches may be taken. These approaches include increasing cell area to avoid design rule violation, taking more metal routing resource to minimize design rule violation, increasing the usage in the chip area to solve the auto placement and route problem, sacrificing poly critical dimension (CD) control to lower the usage rate in metallization layer 2 (M2), and reducing the sizes of some of the transistors to less-than-desirable-values to lower the usage rate in M2.
To explain the above-discussed problems, FIG. 1A is illustrated to show an exemplary conventional layout of a portion of a gate array device, which includes polysilicon lines 102 forming PMOS transistors with diffusion region 11B, and forming NMOS transistors with diffusion region 12B. It is noted that polysilicon lines 102 are twisted with several turns. In small-scale integrated circuits, particularly 45 nm and below, such twisted polysilicon lines will cause critical dimension (CD) variations. Further, limited by design rules, the twisted polysilicon lines also require more chip areas to allow adequate space between the polysilicon lines 102 and between each of the polysilicon lines 102 and neighboring features.
FIG. 1B is illustrated to show an exemplary conventional layout of a standard cell, which includes PMOS transistor 202 interconnected to NMOS transistor 204. Gate poly 210 extends over active regions 206 and 208. Interconnection port 212 is formed between PMOS transistor 202 and NMOS transistor 204, and is connected to gate poly 210. Metal 214 interconnects the drains of PMOS transistor 202 and NMOS transistor 204. The standard cell layout shown in FIG. 1 suffers from drawbacks when used in very small-scale integrated circuits. It is noted that interconnection port 212 and metal 214 are closely located. For very small-scale integrated circuits, the distance between interconnection port 212 and metal 214 becomes so small, that the layout violates the restricted design rules. Further, at the location gate poly 210 is connected to interconnection port 212, gate poly 210 needs to be wider than the portions directly over active regions 206 and 208, and hence the line width uniformity of gate poly 210 is adversely affected. The possible methods for fixing the problem include shifting interconnection port 212 to the left (which method is referred to as poly jog), or route the connection of the drains of PMOS transistor 202 and NMOS transistor 204 through high-level of metals including metallization layer 2 (M2) or higher, so that metal 214 is not in a same metallization layer as interconnection port 212. However, these methods (such as poly jog) either violate further design rules, or cause the undesirable increase in M2 usage rate. New methods for solving the above-discussed problems are thus needed.